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EM MICROELECTRONIC-MARIN SA -
V6170
Accurate Voltage Window Surveillance and Software Monitoring
Features
n Standby mode, maximum current 35 mA n Reset output guaranteed for V DD voltage down to 1.2 V n Comparator for voltage monitoring, voltage reference 1.17 V n 1.5% voltage reference accuracy at + 25 C 3% voltage reference accuracy for -40 to +85 C n Programmable reset voltage monitoring n Voltage window, high threshold 5.9 V n Programmable power-on reset (POR) delay n Watchdog with programmable time window guarantees a minimum time and a maximum time between software clearing of the watchdog n Time base accuracy 10% n System enable (EN) output offers added security n 3 chip select feed-thru circuit controlled by EN n TTL / CMOS compatible n -40 to +85 C temperature range n DIP8 and SO8 packages
Typical Operating Configuration
VDD V6170 R VIN TCL VSS RES EN GND 100 nF
Description
The V6170 offers a high level of integration by voltage monitoring and software monitoring in an 8 lead package. A comparator monitors the voltage applied at the VIN input comparing it with an internal 1.17 V reference. The power-on reset function is initialized after VIN reaches 1.17 V and takes the reset output inactive after T depending of external resistance. The reset POR output goes active low when the VIN voltage is less than 1.17 V or when V DD is higher than 5.9 V. The RES and EN outputs are guaranteed to be in a correct state for a supply voltage as low as 1.2 V. The watchdog function monitors software cycle time and execution. If the software clears the watchdog too quickly (incorrect cycle time) or too slowly (incorrect execution), it will cause the system to be reset. The system enable output prevents critical control functions being activated until software has successfully cleared the watchdog three times. Such a security could be used to prevent motor controls being energized on repeated resets of a faulty system.
Fig. 1
Pin Assignment
DIP8 / SO8
EN RES TCL VSS V6170
VIN R VDD NC
Applications
n n n n n Industrial electronics Cellular telephones Security systems Battery powered products Automotive electronics
Fig. 2
1
V6170
Absolute Maximum Ratings
Parameter Maximum voltage at VDD Minimum voltage at VDD Max. voltage at any signal pin Min. voltage at any signal pin Storage temperature Electrostatic discharge max. to MIL-STD-883C method 3015 Max. soldering conditions Symbol Conditions VDDmax VDDmin VMAX VMIN TSTO VSmax TSmax VSS + 8 V VSS - 0.3 V VDD + 0.3 V VSS - 0.3 V -65 to+150 C 1000 V 250 C x 10 s
operation can only occur when all terminal voltages are kept within the supply voltage range. Unused inputs must always be tied to a defined logic voltage level.
Operating Conditions
Parameter Operating temperature Supply voltage1) RES & EN guaranteed2) Comparator input voltage RC-oscillator programming
1)
Symbol Min. Typ. Max. Units s -40 +85 TA C 1.2 7 VDD V 1.2 VDD V VIN R 0 10 VDD 1000 V k
Table 1 Stresses above these listed maximum ratings may cause permanent damage to the device. Exposure beyond specified operating conditions may affect device reliability or cause malfunction.
Table 2
A 100 nF decoupling capacitor is required on the supply voltage VDD for stability. RES must be pulled up externally to VDD even if it is unused. (Note: RES and EN are used as inputs by EM test)
Handling Procedures
This device has built-in protection against high static voltages or electric fields; however, anti-static precautions must be taken as for any other CMOS component. Unless otherwise specified, proper
2)
Electrical Characteristics
3 V DD 5.5 V, C = 100 nF, TA = -40 to +85 C, unless otherwise specified
Parameter Supply current in standby mode Supply current RES and EN Output Low Voltage
Symbol ISS ISS VOL VOL VOL VOL VOH VOH VOH VIL VIH ILI RVIN VREF VREF VREF VHY1 VHIGH VHIGH VHY2
Test Conditions REXT = don't care, TCL = V DD, VIN = 0 V REXT = 100 k, I/Ps at V DD , O/Ps 1 M to VDD VDD = 4.5 V, IOL = 20 mA VDD = 4.5 V, IOL = 8 mA VDD = 2.0 V, IOL = 4 mA VDD = 1.2 V, IOL = 0.5 mA VDD = 4.5 V, IOH = -1 mA VDD = 2.0 V, IOH = -100 A VDD = 1.2 V, IOH = -30 A 3V VDD 5.5 V 3V VDD 5.5 V VSS VTCL VDD TA = +25 C TA = -20 to +70 C TA = +25 C TA = -40 to +70 C
Min.
Typ. 24 55 0.4 0.2 0.2 0.06
Max. 35 100
Units A A V V V V V V V V V A M V V V mV V V mV
0.4 0.4 0.2
EN Output High Voltage TCL and VIN TCL and Input Low Level TCL and Input High Level Leakage current TCL input VIN input resistance Comparator reference 1) Comparator hysteresis 1) Level detector of V DD 2) Hysteresis2)
1)
3.5 1.8 1.0 VSS 2.0 1.148 1.123 1.123 5.78 5.60
4.1 1.9 1.1
0.05 100 1.170 2 5.95 50
0.8 VDD 1 1.200 1.218 1.222 6.12 6.30
2)
The comparator reference is the power-down reset threshold. The power-on reset threshold equals the comparator Table 3 reference voltage plus the comparator hysteresis (see Fig. 5). The level detector of VDD (VHIGH) is the level when VDD is rising. The level detector when VDD is falling equals VHIGH minus the
hysteresis (V HY2) (see Fig. 5).
2
V6170
ISS Standby versus at VDD = 5.5 V
30 28 26 24 22 20 18 16 14 12 10 -40 -30 -20 -10 0 10 20 TA [C] 30 40 50 60 70 80 Fig. 3
Timing Characteristics
V DD = 5.0 V 3%, C = 100 nF, TA = -40 to +85 C, unless otherwise specified
ISS [A]
Parameter Propagation delays: TCL to Output Pins VIN sensitivity Logic Transition Times on all Output Pins Power-on Reset delay Watchdog Time Open Window Percentage Closed Window Time Open Window Time Watchdog Reset Pulse TCL Input Pulse Width
Symbol TDIDO TSEN TTR TPOR TWD OWP TCW TCW TOW TOW TWDR TWDR TTCL
Test Conditions
Min.
Typ. 250 5 30 100 100 0.2 TWD 0.8 TWD 80 0.4 TWD 40 TWD / 40 2.5
Max. 500 20 100 110 110 88 44
Units ns s ns ms ms ms ms ms ns Table 4
Load 10 k, 50 pF REXT = 118 k, 1% REXT = 118 k, 1% REXT = 118 k, 1% REXT = 118 k, 1% REXT = 118 k, 1%
1 90 90 72 36 150
Timing Waveforms
Watchdog Timeout Period
TWD = TPOR - OWP - 20% + OWP + 20% Condition: REXT = 118 k
Watchdog timer reset
TCW - closed window 80
TOW - open window t [ms] 100 120 Fig. 4 3
V6170
Voltage Monitoring
V VHIGH VHY2 Condition: VDD 3 V No timeout TSEN VHY1 TSEN TPOR RES TSEN TSEN TPOR TSEN TSEN TPOR TSEN
VREF
Fig. 5
Timer Reaction
TCW TCL RES EN TOW TCW TCW+TOW TCW+TOW TTCL TWOR
1 2 3
TOW
Condition: V IN > VREF after power-up sequence TCW TCW+TOW
3 correct TCL services EN goes active low - Watchdog timer reset
Timeout Fig. 6
Combined Voltage and Timer Reaction
VIN VREF Condition: VDD 3 V
TPOR=TWD TCL
TOW TCW+TOW
TCW
RES EN TCL too early - Watchdog timer reset 4
1 2 3
3 correct TCL service EN goes active low Fig. 7
V6170
Block Diagram
Comparator
-
+ Voltage Reference
Enable Logic
EN
VREF
-
+
Comparator
Reset Control
RES
VIN
R
Current Controlled Oscillator
Timer
Open drain output RES Fig. 8
TCL
Pin Description
Pin Name
1 2 3 4 5 6 7 8 EN RES TCL VSS NC VDD R VIN
Function
Push-pull active low enable output Open drain active low reset output. RES must be pulled up to V DD even if unused Watchdog timer clear input signal GND terminal No connection Voltage supply REXT input for RC oscillator tuning Voltage comparator input Table 5
POR delay allows the microprocessor's crystal oscillator time to start and stabilize and ensures correct recognition of the reset signal to the microprocessor. The RES output goes active low generating the powerdown reset whenever VIN falls below VREF. The sensitivity or reaction time of the internal comparator to the voltage level on V IN is typically 5 ms.
Voltage Window
The reset output (RES) is inactive when V IN is higher than VREF and when VDD is lower than VHIGH. If VIN is less than VREF or V DD higher than V HIGH, the reset output goes active low (see Fig. 5).
Timer Programming
The on-chip oscillator needs an external resistor REXT connected between the R pin and VSS (see Fig. 9). It allows the user to adjust the power-on reset (POR) delay, watchdog time TWD and with this also the closed and open time windows as well as the watchdog reset pulse width (TWD/40). With R EXT = 118 kW, the typical delays are: - Power-on reset delay: TPOR is 100 ms - Watchdog time: TWD is 100 ms - Closed window: TCW is 80 ms - Open window: TOW is 40 ms - Watchdog reset: TWOR is 2.5 ms Note the current consumption increases as the frequency increases.
Functional Description
VIN Monitoring
The power-on reset and the power-down reset are generated as a response to the external voltage level on the VIN input. The external voltage level is typically obtained from a voltage divider as shown in Fig. 9. The user defines an external voltage divider to set the desired threshold level for power-on reset and powerdown reset in his system. The internal comparator reference voltage is typically 1.17 V. At power-up the reset output (RES) is held low (see Fig. 5). When VIN becomes greater than VREF, the RES output is held low for an additional power-on reset (POR) delay wich is equal to the watchdog time TWD (typically 100 ms with an external resistor of 118 kW connected at R pin). The POR delay prevents repeated toggling of RES even if V IN and the INPUT voltage drops out and recovers. The
Watchdog Timeout Period Description
The watchdog timeout period is divided into two parts, a "closed" window and an "open" window (see Fig. 4) and is defined by two parameters, TWD and the Open Window Percentage (OWP). The closed window starts just after the watchdog timer 5
V6170
resets and is defined by TCW = TWD - OWP(TWD ). The open window starts after the closed time window finishes and lasts till TWD + OWP(TWD). The open window time is defined by TOW = 2 x OWP(TWD). For example if TWD = 100 ms (actual value) and OWP = 20% this means the closed window lasts during first the 80 ms (TCW = 80 ms = 100 ms - 0.2 (100 ms)) and the open window the next 40 ms (TOW = 2 x 0.2 (100 ms) = 40 ms). The watchdog can be serviced between 80 ms and 120 ms after the timer reset. However as the time base is 10% accurate, software must use the following calculation for servicing signal TCL during the open window: Related to curves (Fig. 10 to Fig. 20), especially Fig. 19 and Fig. 20, the relation between T and REXT could WD easily be defined. Let us take an example describing the variations due to production and temperature: 1. Choice, TWD = 26 ms. 2. Related to Fig. 20, the coefficient (T WD to R EXT) is 1.125 where R EXT is in kW and TWD in ms. 3. REXT (typ.) = 26 x 1.125 = 29.3 kW. 4. 26 ms at +25 C
a)
watchdog too quickly (incorrect cycle time) or too slowly (incorrect execution), it will cause the system to be reset. If the software is stuck in a loop which includes the routine to clear the watchdog, a conventional watchdog will not reset the system even though the software is malfunctioning; the V6170 will generate a system reset because the watchdog is cleared too quickly. If no TCL signal is applied before the closed and open windows expire, RES will start to generate square waves of period (TCW + TOW + TWDR). The watchdog will remain in this state until the next TCL falling edge appears during an open window, or until a fresh power-up sequence. The system enable output, EN, can be used to prevent critical control functions being activated in the event of the system going into this failure mode (see section "Enable - EN Output"). The RES output must be pulled up to VDD even if the output is not used by the system (see Fig. 9).
Combined Voltage and Timer Action
The combination of voltage and timer actions is illustrated by the sequence of events shown in Fig. 7. On power-up, when the voltage at VIN reaches VREF, the power-on-reset, POR, delay is initialized and holds RES active for the time of the POR delay. A TCL pulse will have no effect until this power-on reset delay is completed. After the POR delay has elapsed, RES goes inactive and the watchdog timer starts acting. If no TCL pulse occurs, RES goes active low for a short time TWDR after each closed and open window period. A TCL pulse coming during the open window clears the watchdog timer. When the TCL pulse occurs too early (during the closed window), RES goes active and a new timeout sequence starts. A voltage drop below the VREF level for longer than typically 5 ms, overrides the timer and immediately forces RES active and EN inactive. Any further TCL pulse has no effect until the next power-up sequence has completed.
(26 - 10% = 23.4 ms) (26 + 10% = 28.6 ms) a)
b)
(23.4 - 5% = 22.2 ms)
(28.6 + 5% = 30.0 ms)b)
min.: (30.0 - 20% = 24.0 ms) max.: (22.2 + 20% = 26.7 ms)
Typical TCL period of (24.0 + 26.7) / 2 = 25.4 ms The ratio between TWD = 26 ms and the (TCL period) = 25.4 ms is 0.975. Then the relation over the production and the full temperature range is, TCL period = 0.975 x TWD 0.975 x R EXT or TCL period = , as typical value. 1.125 a) While PRODUCTION value unknown for the customer when R EXT 118 kW. b) While operating TEMPERATURE range -40 C TA +85 C. 5. If you fixed a TCL period = 26 ms 26 x 1.125 REXT = 30 kW 0.975 If during your production the TWD time can be measured, at TA = +25 C and the mC can adjust the TCL period, then the TCL period range will be much larger for the full operating temperature.
Enable - EN Output
Timer Clearing and RES Action
The watchdog circuit monitors the activity of the processor. If the user's software does not send a pulse to the TCL input within the programmed open window timeout period, a short watchdog RES pulse is generated which is equal to TWD/40 = 2.5 ms typically (see Fig. 6). With the open window constraint, new security is added to conventional watchdogs by monitoring both software cycle time and execution. Should software clear the 6
The system enable output, EN, is inactive always when RES is active and remains inactive after a RES pulse until the watchdog is serviced correctly 3 consecutive times (ie. the TCL pulse must come in the open window). After three consecutive services of the watchdog with TCL during the open window, the EN goes active low. A malfunctioning system would be repeatedly reset by the watchdog. In a conventional system critical motor controls could be energized each time reset goes inactive (time allowed for the system to restart) and in this way the electrical motors driven by the system could function out of control. The V6170 prevents the above failure mode by using the EN output to disable the motor controls until software has successfully cleared the watchdog three times (ie. the system has correctly restarted after a reset condition).
V6170
Typical Application
VDD
Supply voltage 100 nF R1 100 k Address Decoder
R 100 k
V6170
VIN TCL P RES R2 Motor EN Controls GND
VSS
RES EN
Fig. 9
7
V6170
TWD versus Temperature at 5 V
10'000 R = 10 M
TWD versus R at 5 V
10'000
1000 R = 1 M
1000
TWD [ms]
TWD [ms]
100 R = 100 k
100 -40 to 85 C 10
10
R = 10 k
1 -40 -20 TA [C] +25 +85 Fig. 10
1
1
10
100 R [k]
1000
10'000 Fig. 11
TWD versus V DD at TA = + 25 C
10'000 R = 10 M
TWD versus R at TA = + 25 C
10'000
1000 R = 1 M TWD [ms] TWD [ms] 100 R = 100 k
1000
100
3V 4.5 V 5V 5.5 V
R = 10 k 10 3.0 4.0 VDD [V] 5.0 Fig. 12 10 10 100 R [k] 1000 10'000 Fig. 13
8
V6170
TWD versus R at TA = +25 C 10'000
1000
TWD [ms]
100
3V 4.5 V 5V 5.5 V
10 10 100 1000 10'000
R [k]
Fig. 14
9
V6170
TWD versus V DD at TA = + 85 C
10'000 R = 10 M
TWD versus R at TA = + 85 C
10'000
1000 R = 1 M TWD [ms] TWD [ms] 100 R = 100 k
1000
100
3V 4.5 V 5V 5.5 V
R = 10 k 10 3.0 4.0 VDD [V] 5.0 Fig. 15
10
10
100 R [k]
1000
10'000 Fig. 16
TWD versus V DD at TA = - 40 C
10'000 R = 10 M
TWD versus R at TA = - 40 C
10'000
1000 R = 1 M 1000
TWD [ms]
100 R = 100 k
TWD [ms]
100 10 R = 10 k
3V 4.5 V 5V 5.5 V
1
10 3.0 4.0 VDD [V] 5.0 Fig. 17
10
100 R [k]
1000
10'000 Fig. 18
10
V6170
TWD Coefficient versus REXT at TA = + 25 C
1.00 0.98 0.96 0.94 TWD Coefficient 0.92 0.90 0.88 0.86 0.84 0.82 0.80 10 100 REXT [k] 1000 Fig. 19
REXT Coefficient versus TWD at TA = + 25 C
1.24 1.22 1.20 1.18 REXT Coefficient 1.16 1.14 1.12 1.10 1.08 1.06 1.04 1.02 1.00 10 100 TWD [ms] 1000 Fig. 20 11
V6170
Ordering Information
The V6170 is available in the following packages Type Package V6170 8P DIP8 V6170 8S SO8 When ordering please specify complete part number.
EM Microelectronic-Marin SA cannot assume any responsibility for use of any circuitry described other than entirely embodied in an EM Microelectronic-Marin SA product. EM Microelectronic-Marin SA reserves the right to change the circuitry and specifications without notice at any time. You are strongly urged to ensure that the information given has not been superseded by a more up-to-date version.
(c) 2000 EM Microelectronic-Marin SA, 10/00, Rev. D/334
12 EM Microelectronic-Marin SA, CH - 2074 Marin, Switzerland, Tel. (+41) 32 - 755 51 11, Fax (+41) 32 - 755 54 03

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